搜索资源列表
RAM_test
- ADSPTS201相关程序，总线方式、DMA方式读写片外SDRM和FPGA内部RAM数据 -ADSPTS201 procedures, the bus mode, DMA mode and the FPGA to read and write chip internal RAM data SDRM
DoubleRAM
- actel fpga kit 双端口RAM 实验-actel fpga kit dual-port RAM test
ram_fpgavhdl
- fpga vhdl实现一个标准双端口ram，可以作为单端口或者双端口用 -fpga vhdl achieve a standard dual-port ram, can be used as a single port or dual port with a
m4k-example
- FPGA中M4K的使用例子，比如rom ram-the example to useing M4K in FPGA
PseudoHC11_MCU
- This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.-This extensive proyect turns an
ygyTest
- 利用开源网站上的8051核，在Spartan 3A开发板上实现成功，开发环境是Xilinx ISE Design Suite 12.3，顶层文件基于原理图开发，扩展了外部ROM和RAM，且更改了地址宽度-implment the mc8051 IP in spartan-3A FPGA starten kit.
spram
- 基于altera fpga 的单口ram ip核的应用实例，包含整个工程和moselsim仿真，数据，写使能，地址都是用模块来产生的。-Altera fpga single port ram the ip core application instance, contains the entire engineering and moselsim of simulation data, Write Enable, addresses are generated by the module.
cpu
- 用FPGA实现了CPU中RAM,ROM等功能，设计比较完整-FPGA Implementation of a CPU, RAM, ROM, function, design is more complete
how_to_use_RAM
- actel的fpga ram核使用手册,想入手学习ram的同学可以参考一下。-the techManual of actel fpga ram ipcore，and the beginner can use it easily.
Port-RAMs
- 介绍双口ram功能，进一步了解在fpga上怎么设计一个双口ram-Introduced the dual-port ram function to learn more about the fpga on how to design a dual port ram
ug_ram_rom
- ALTERA公司的FPGA中RAM,ROM的使用手册和帮助-ALTERA' s FPGA RAM, ROM user manual and help
FIFO
- FPGA内设计同步FIFO和异步FIFO，以及双口RAM的方法,FIFO设计的经验之谈，非常经典。-Synchronous FIFO and asynchronous FIFO, and dual-port RAM within the FPGA design,FIFO design rule of thumb, very classic.
ActelFPGA_RAM_an
- FPGA下开发RAM的手册，与FPGA自带的说明不同-FPGA development manual of RAM, comes with instructions and FPGA
test
- The design shows how to use Dual port RAM in FPGA design
jpeg_hardware.tar
- 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V
verilog--sram
- ram的fpga应用，用verilog语言实现，适用于cyclone 2系列-ram the fpga application verilog language applicable to cyclone 2
Using-the-Virtex-Block-SelectRAMP
- The Virtex™ series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+™ memory can be independently configured as a read/write port, a read port, o
emif
- EMIF字符型设备驱动，实现了dm368与FPGA之间的通信，把FPGA当着dm368的一个ram往里面写数据和向外发数据。-The driver of EMIF .
lab5_files
- 关于FPGA ROM与RAM的分析应用及源码-Applications and source code analysis of the FPGA ROM and RAM
GX_BOARD
- FPGA设计参考电路（SDRAM,SD卡，USB，数码管，I2C,ram）-FPGA design reference circuit (SDRAM, SD card, USB, digital tube, I2C, ram)